1. Field of the Invention
The present invention relates to a semiconductor device in which voltage at a control electrode causes a current conducting state or a current blocking state.
2. Description of the Prior Art
FIG. 32 shows a cross section of a conventional semiconductor device called EST (Emitter Switched Thyristor). An n.sup.- layer 2 is formed on a p.sup.+ substrate 1 by epitaxial growing, a p diffusion region 3 is formed on a surface of the n.sup.- layer 2, and further, n.sup.+ diffusion regions 4a and 4b are formed separated from each other on a surface of the p diffusion region 3.
On the surface of the p diffusion region 3 between the n.sup.+ diffusion regions 4a and 4b, a gate electrode 5a lies insulated from the surrounding by an insulating film 6. Also, on the surface of the p diffusion region 3 between the n.sup.+ diffusion region 4b and the n.sup.- layer 2, a gate electrode 5b lies insulated from the surrounding by an insulating film 6. An Al--Si electrode 7 is in contact with the p diffusion region 3 and the n.sup.+ diffusion region 4a, and a metal electrode 8 is in contact with a p.sup.+ substrate 1. An equivalent circuit of the semiconductor device as configured above is shown in FIG. 33. In FIG. 33, a diffusion resistance extending from a part in contact with the electrode 7 up to the bottom of the electrode 5a is denoted by a resistance R1. Also, a diffusion resistance extending from the bottom of the electrode 5a up to the bottom of the electrode 5b is denoted by a resistance R2.
An npn transistor B11 has an emitter of the n.sup.+ diffusion region 4a, a base of the P diffusion region 3, and a collector of the n.sup.+ diffusion region 4b and n.sup.- layer 2, while an npn transistor B12 has an emitter of the n.sup.+ diffusion region 4b, a base of the p diffusion region 3, and a collector of the n.sup.- layer 2. A pnp transistor B13 has an emitter of the p.sup.+ substrate 1, a base of the n.sup.- layer 2, and a collector of the p diffusion region 3.
An n channel MOS transistor M11 has a source of the n.sup.+ diffusion region 4a, a drain of the n.sup.+ diffusion region 4b, a gate of the electrode 5a, and a back gate of the p.sup.+ diffusion region 3, while an n channel MOS transistor M12 has a source of the n.sup.+ diffusion region 4b, a drain of the n.sup.- layer 2, a gate of the electrode 5b, and a back gate of the p diffusion region 3.
Since the electrodes 5a and 5b are generally used at the same potential in such a semiconductor device, hereinafter "electrode 5" indicates both of them in block in some case. When a potential at the electrode 8 is raised with the electrodes 7 and 5 at the same potential, a depletion layer extends from a pn junction between the p diffusion region 3 and the n.sup.- layer 2 to retain voltage. In general, the p.sup.+ substrate 1 and a portion where the n.sup.- layer 2 is in contact with the p.sup.+ substrate are often designed as n.sup.+ so as to prevent an end of the depletion layer from reaching the p.sup.+ substrate 1 and punching through.
When voltage at the electrode 5 related to the electrode 7 is raised in the above mentioned situation, the p diffusion region 3 just below the electrode 5 causes an n inversion, and consequently, the transistors M11 and M12 turn on and the EST also turns on. FIG. 34 shows a flow of carriers in such an ON-state. In FIG. 34, a flow of electrons is shown by an arrow of broken line while a flow of holes is shown by an arrow of solid line.
Electrons flow from the n.sup.+ diffusion region 4a through the n.sup.+ diffusion region 4b to the n.sup.- layer 2 while holes are introduced from the p.sup.+ substrate 1 to the p diffusion region 3, and the transistor B13 turns on. Generally, holes flow in accordance with an electron current density, and therefore, a relatively large amount of holes enter the p diffusion region 3 from the surrounding of the n inversion layer just below the electrode 5b. Many of the holes flowing in are led in a horizontal direction (a direction orthogonal to a thicknesswise direction) in the p diffusion region 3 and reach the electrode 7.
At this time, the p diffusion region 3 acting as the resistances R1 and R2 causes a potential at the p diffusion region 3 just below the n.sup.+ diffusion region 4b to rise related to the electrode 7. On the other hand, the n.sup.+ diffusion region 4b is linked through the n.sup.+ diffusion region 4a and the inversion layer just below the electrode 5a to the electrode 7, potential rising at the n.sup.+ diffusion region 4b is considerably small, compared with the above-mentioned potential rising at the p diffusion region 3. Thus, as holes flowing in the p diffusion region 3 increase, an area between the n.sup.+ diffusion region 4b and the p diffusion region 3 is forward-biased, and electrons are introduced via the p diffusion region 3 into the n.sup.- layer 2 to turn the transistor B12 on.
The diffusion region 4b, p diffusion region 3, n.sup.- layer 2, and p.sup.+ substrate 1 are components of a thyristor consisting of the transistors B12 and B13, and the thyristor is actuated when hole current increases to some extent or over. Actuation of the thyristor causes a current density in an ON-state of the EST to rise, and its ON-resistance drops.
Then, the n inversion layer just below the electrode 5a is extinguished when voltage at the electrode 5 is reduced, and the transistor M11 which is positioned in series with the thyristor consisting of the transistors B12 and B13 turns off. Consequently, electrons introduced from the emitter of the n.sup.+ diffusion region 4b of the transistor B12 into the base of the p diffusion region 3 cannot be supplied, and a thyristor operation stops. The holes which has been led in the n.sup.- layer 2 in advance flow away from the p diffusion region 3 to the electrode 7. In this way, the EST turns off again.
The conventional semiconductor device is configured as mentioned above, and the thyristor consisting of the transistors B11 and B13 is actuated when current between the electrodes 7 and 8 is increased. When the thyristor is actuated in this portion, the electrode 5 comes into a current uncontrollable state (latch-up state). To avoid this, a device design where the resistance R1 takes a value as small as possible should be made so that voltage drop due to hole current flowing in the resistance R1 does not cause the transistor B11 to operate. Specifically, it is necessary to reduce the resistance R1 to make current between the electrodes 7 and 8 controllable by the electrode 5 (maximum controllable current) much larger.
It is also possible forming the p diffusion region 3 just below the n.sup.+ diffusion region 4a deeply to reduce the resistance R1, and accordingly, a rate of holes flowing only in the p diffusion region 3 deeply formed to holes led from the p.sup.+ substrate 1 into the electrode 7 rises. The former holes do not contribute to the operation of the thyristor consisting of the transistors B12 and B13, and therefore, a minimum current value (holding current) to retain the thyristor operation consequently becomes large. Thus raised maximum controllable current often causes adverse effects to other characteristics.
On the other hand, there is a limit to reduce a resistance rate of the p diffusion region 3.